The present invention relates to an electromagnetic interference (EMI) analysis method and apparatus, and more particularly, to a method capable of carrying out an EMI analysis at a high speed with high precision for a large-scaled high-speed driving LSI (Large-Scaled Semiconductor Integrated Circuit). The method also allows for analyzing an electromagnetic interference in the case in which there is no current information.
The utilization range of the LSI has been enlarged to a communication apparatus such as a mobile telephone, general home products, toys and automobiles as well as a computer. On the other hand, there is a problem in that electromagnetic interference generated from these products causes radio interference noise for receivers contained in, for example, a television or a radio and/or the malfunction of other systems. Countermeasure for preventing such interference, such as, filtering or shielding has also been attempted to solve such problems. However, the noise suppression of an LSI package has been highly demanded as a result of an increase in the number of components, an increase in a cost and the difficulty to take effective countermeasure.
Under the circumstances, the LSI is positioned as a key device in each product, and an increase in the scale and speed of the LSI has been required to maintain the competition power of the product. In order to meet these requirements with a reduction in the product cycle, it is necessary to automate the LSI design. The necessity of employing a synchronous design has been increased as the present conditions for introducing a design automation technology.
As shown in FIG. 30, conventionally, there has been proposed a method in which an LPE (layout element extraction) processing for creating a netlist (a circuit connection information file) including a parasitic resistance and a capacitance component is executed by using an EMI dedicated library 3101 and layout information 3102 which are obtained by previously characterizing the internal capacitance and input capacitance of a cell (step 3103) and the total capacitance of a block is calculated (step 3105).
Similarly, a block netlist 3106 is also subjected to the LPE, and the supply current of the block is calculated under the condition of no resistance of the power supply line and no supply capacitance of the power supply line (step 3107), and thereby, the current on the power supply line can be obtained.
Moreover, the current model of the total block capacitance and supply current is connected to a power netlist 3104 which is subjected to the LPE in the same manner.
The connection information is subjected to a transistor level simulation, thereby estimating an EMI noise (step 3109).
Thus, an EMI spectrum 3110 is obtained.
However, when utilizing this method, there is a problem in that a special library for capacitance estimation is required.
Moreover, since a transistor level simulator is used for the supply current calculation, there is a problem in that a very long time is required for the operation.
Furthermore, since the LEP is carried out including a power supply, a very long time is required for the operation.
In addition, the power netlist, the capacitance information and the supply current information are collectively subjected to the transistor level simulation. For this reason, there is a problem in that a very long time is also required for this operation.
Therefore, in order to increase the speed of the operation, there has been proposed a method of extracting an RLC by means of an impedance analyzer.
In this method, as shown in FIG. 31, R3203, L3204 and C3205 are calculated from LSI information 3201 by using an impedance analyzer 3202. Then, these values, a supply current spectrum 3210 obtained by carrying out a supply current estimation 3209 on a gate level from a load capacitance 3206, a gate level netlist 3207 and a test vector 3208, and the supply current spectrum 3210 and the RLC are used to carry out an EMI estimation (step 3211) so that an EMI spectrum 3212 is obtained.
In this method, the supply current can be estimated on the gate level. Therefore, the operation can be carried out at a high speed.
Moreover, since the RLC information capable of being obtained from an actual chip at a high speed is used, the speed of the processing can be increased.
Furthermore, in the EMI estimation, the frequency response of a power measuring system netlist determined from the RLC information is multiplied by the supply current spectrum without using the transistor level simulation. Therefore, the speed of the operation can be increased.
In addition, an analysis is carried out based on information to be used in a standard gate level verification flow. Consequently, special processing and particular information are not required.
However, this method is based on the results of actual measurements. For this reason, there has conventionally been a problem in that a method of accurately predicting the RLC in the design stage cannot be proposed.
Although the speed is higher than that of the transistor level simulation, the gate level simulation is still required. Therefore, there has been a problem in that a long time is required for the operation.
Moreover, there has been a problem in that the prediction is difficult in a floor plan stage in which a netlist is not determined.
Under the circumstances described above, in the LSI design, it is apparent that the EMI should be estimated as early as possible and the design should be changed in the early stages when necessary in order to obtain the shortest technique for easily carrying out reliable LSI design. Utilizing the known techniques, however, there is no method of carrying out the EMI analysis in the floor plan stage prior to the LSI design.
The invention has been made in consideration of the foregoing problems and it is an object of the present invention to provide an electromagnetic interference analysis method and apparatus which can carry out an EMI analysis in the early stage of a design and which can reflect the information of a circuit and a package on a calculation while performing a high-speed analysis, thereby evaluating the electromagnetic interference of an LSI on a simulation in actual time.
In particular, the invention has an object to provide a method capable of carrying out an EMI analysis in a floor plan stage without calculating supply current information.
The invention provides a method of analyzing an electromagnetic interference amount of an LSI, including an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.
According to such a structure, the equivalent impedance information is calculated from the circuit information and the package information without calculating the supply current information from the circuit information of the LSI chip, and a capacitance countermeasure correction is then carried out. Therefore, an electromagnetic interference analysis can easily be performed at a high speed. Moreover, the analysis can be carried out based on only the circuit information in the early design stage. Consequently, a chip area, a power supply or a package can easily be changed, the degree of freedom for taking an electromagnetic interference countermeasure can be increased and electromagnetic interference can be reduced.
Moreover, it is desirable that the equivalent impedance information calculating step should include a first extracting step of extracting a chip area, a power pad position and power supply information from the circuit information and a second extracting step of extracting a package type from the package information, and equivalent impedance information should be calculated and estimated based on the information obtained at the first and second extracting steps.
According to such a structure, the chip area, the power pad position and the power supply information are extracted from the circuit information. Once this information is determined, the equivalent impedance can be calculated. Thus, it is possible to easily obtain desirable information.
It is desirable that the circuit information should include floor plan information.
According to such a structure, the equivalent impedance is calculated based on the floor plan information. Therefore, the electromagnetic interference analysis can be carried out in the initial stage of a circuit design, the design can be easily executed again, and an optimized design can be realized without restriction.
It is desirable that the circuit information should include layout information.
According to such a structure, layout data has a high degree of concreteness. Therefore, equivalent impedance information having high precision can be calculated. Based on the value, the electromagnetic interference analysis is carried out. If the electromagnetic interference analysis is to be performed in a layout design stage, consequently, it is possible to carry out the electromagnetic interference analysis with higher precision and higher reliability. Thus, the equivalent impedance information is calculated from the circuit information on a layout level and the electromagnetic interference analysis is carried out based on the value. Therefore, if the electromagnetic interference analysis is to be performed in such a stage that a layout is once fixed, it is possible to carry out the electromagnetic interference analysis with higher precision and higher reliability.
It is desirable that the circuit information should include netlist information.
According to such a structure, it is possible to carry out the electromagnetic interference analysis with higher precision. Moreover, the number of transistors can be known by only a netlist without floor plan information, and an area (a resistance) can be estimated based on the number of transistors. Furthermore, it is also possible to estimate a capacitance from the connection information of the netlist.
Moreover, it is desirable that the netlist information should include circuit information on a function level.
According to such a structure, it is possible to further reduce an operation time as compared with circuit information on a gate level. Furthermore, it is possible to calculate an equivalent impedance adapted to an LSI design phase.
It is desirable that the netlist information should include circuit information on a gate level.
According to such a structure, it is possible to further reduce an operation time as compared with circuit information on a transistor level. Furthermore, it is possible to calculate an equivalent impedance adapted to an LSI design phase.
It is desirable that the netlist information should include circuit information on a transistor level.
According to such a structure, it is possible to easily calculate an equivalent impedance from the circuit information on the transistor level in consideration of a device component. More specifically, the netlist on the transistor level is extracted from the layout data, and agate capacitance, a wiring capacitance, a power capacitance and an MOS capacitance (a capacitance between a power line and a grounding conductor) are calculated. Consequently, it is possible to easily calculate equivalent impedance information.
It is desirable that the equivalent impedance information calculating step should estimate a memory block as a capacitance from the circuit information so as to be executed.
According to such a structure, data using a memory block as a capacitance are utilized. Therefore, it is possible to calculate an equivalent impedance in consideration of a parasitic component as well. The electromagnetic interference analysis can be carried out in the initial stage of a circuit design, the design can easily be carried out again and an optimized design can be realized without restriction.
It is desirable that the equivalent impedance information calculating step should serve to estimate a capacitance in consideration of an activation ratio.
According to such a structure, a device element and a parasitic element are extracted as a gate capacitance, a wiring capacitance, a power capacitance and an MOS capacitance (a gate capacitance between a power line and a grounding conductor). The element is not operated as capacitance when the element is set in an operation state (active). Therefore, a capacitance value is multiplied by an activation ratio xcex2 so that an equivalent capacitance having higher precision can be obtained. The activation ratio of a cell or element can be obtained based on the dynamic analysis of an operation/non-operation.
Furthermore, it is desirable that the equivalent impedance information calculating step should include a step of estimating a resistance value from the circuit information.
According to such a structure, it is possible to easily carry out an EMI analysis with high precision.
Moreover, it is desirable that the equivalent impedance information calculating step should include a step of extracting circuit connection information from the circuit information, and furthermore, creating circuit connection information in which an active element is substituted for a predetermined resistance and calculating an equivalent resistance.
According to such a structure, the resistance of a power supply can be estimated very easily, and the EMI analysis can readily be carried out with higher precision.
According to such a structure, a LPE for a power supply line is carried out and a transistor connecting terminal is connected through a resistor (an ON-state resistor and a cutoff resistor), for example, and an equivalent resistance is estimated with a current amount on the power supply, for example. Consequently, it is possible to easily obtain equivalent impedance information without supply current information. Thus, the electromagnetic interference analysis can be carried out.
Moreover, it is desirable that the equivalent impedance information calculating step should include a step of estimating a resistance value based on a chip area from the circuit information.
If the chip area is determined, a coefficient obtained from the sheet resistance of a circuit pattern and previously measured statistic information is multiplied so that an equivalent resistance can easily be obtained in a floor plan stage.
It is desirable that the equivalent impedance information calculating step should include a step of changing inductance information for a wire length into a database, a step of calculating the wire length from the circuit information and the package information, and a step of extracting the inductance information changed into the database from the wire length, thereby estimating an inductance. Incidentally, the wire is lead frame and wire bonding.
An inductance obtained by a wire is predominant. Therefore, if the inductance for the wire length is previously changed in a database to obtain the wire length from a package pin and a power pad position and to estimate the inductance from the database, it is possible to estimate the inductance very easily with high precision.
It is desirable that the method should include a noise estimating step of estimating an EMI noise based on an equivalent impedance obtained at the equivalent impedance information calculating step.
According to such a structure, it is possible to estimate the EMI noise without obtaining the supply current information.
Moreover, it is desirable that the noise estimating step should include a step of calculating a frequency response characteristic of the LSI from the equivalent impedance and the circuit information and a step of estimating an EMI noise of the LSI in a specific frequency band based on the frequency response characteristic.
According to such a structure, the frequency response characteristic of the LSI is calculated from the equivalent impedance and the circuit information without obtaining the supply current information and the EMI noise is thereby estimated. Therefore, it is possible to easily carry out the EMI analysis with high precision in the initial stage of a design. Consequently, the design can easily be changed, and furthermore, uselessness can be eliminated.
It is desirable that the noise estimating step should include a step of calculating an offset value based on a clock frequency and an estimated consumption power and a step of multiplying the frequency response characteristic by the offset value.
According to such a structure, it is possible to easily carry out a noise estimation.
It is desirable that the method should further include a correcting step of carrying out a correction in order to optimize an EMI noise based on the equivalent impedance.
According to such a structure, the correction for optimizing the EMI noise is carried out depending on the equivalent impedance information thus obtained. Consequently, the EMI noise can be suppressed without trial and error. Thus, an optimization can easily be realized.
Moreover, it is desirable that the correcting step should include a step of correcting a power terminal position, a package type and a wire length in order to correct an inductance estimated at the estimating step.
According to such a structure, it is preferable that the inductance estimated at the estimating step should be optimized by correcting the power terminal position, the package type and the wire length. Therefore, the EMI noise can be suppressed without an increase in an area and the optimization can easily be realized efficiently.
It is desirable that the correcting step should include a step of correcting a signal wiring capacitance such that a timing has no problem from the capacitance estimated at the estimating step.
According to such a structure, it is preferable that the signal wiring capacitance should be corrected to have no timing delay. Thus, the optimization can easily be realized efficiently.
Furthermore, it is desirable that the step of correcting a signal wiring capacitance should include a step of correcting a signal wiring width, a signal wiring length and a signal wiring path.
The signal capacitance can be regulated based on the wiring width, the wiring length and the wiring path. By correcting these values, therefore, the correction can be carried out very easily.
Moreover, it is desirable that the correcting step should include a power wiring layout correcting step of correcting a power wiring layout such that a voltage drop has no problem.
When the capacitance value is greatly changed, the voltage drop becomes a problem. By adjusting the power wiring layout, however, the correction can be carried out.
It is desirable that the power wiring layout correcting step should include a step of correcting a power path, a power wiring width and a power wiring length.
According to such a structure, the correction of the power wiring capacitance can easily be optimized by the correction of the power path, the power wiring width and the power wiring length.
It is desirable that the correcting step should include a step of correcting a decoupling capacitance.
According to such a structure, the decoupling capacitance for optimizing the EMI noise is corrected depending on the equivalent impedance information thus obtained. Therefore, it is possible to suppress the EMI noise without trial and error. Thus, the optimization can easily be realized.
It is desirable that the correcting step should include a step of correcting a connection relationship between a power supply and a capacitance.
According to such a structure, the magnitude of the equivalent impedance is optimized by only changing the arrangement of the impedance without varying the area of a chip for constituting the impedance. Consequently, the EMI noise can be suppressed without an increase in the area so that the optimization can easily be realized efficiently.
In the method, by directly calculating the equivalent impedance from the circuit information without calculating the supply current information, it is possible to easily carry out the EMI analysis. It is apparent that the method is also effective for the case in which the supply current information is calculated and the EMI analysis is carried out based on the supply current information.
More specifically, in the method of analyzing an electromagnetic interference amount of an LSI, it is also possible to calculate equivalent supply current information sent to a supply current from the circuit information of the LSI chip, to consider, as analysis control information, at least one of the power supply information of a power supply for supplying a current to the LSI chip, the package information of the package of the semiconductor chip and the measuring system information of a measuring system for measuring the characteristic of the semiconductor chip, to estimate, as an equivalent circuit, general information obtained by reflecting the analysis control information on the circuit information and to execute an analysis in accordance with the general information thus estimated.
According to the structure, it is possible to analyze an electromagnetic interference caused by the power supply and the package at a high speed with a small memory and high precision in addition to an electromagnetic interference caused by the circuit of the LSI chip.
Moreover, it is also possible to temporarily determine a power supply for supplying a current to the LSI chip and to include at least one of the power supply information, the package information of the package of the semiconductor chip and the measuring system information of the measuring system for measuring the characteristic of the semiconductor chip, thereby obtaining an equivalent impedance.
Based on the result obtained by the electromagnetic interference analysis method, the circuit information is optimized to reduce an electromagnetic interference. Consequently, it is possible to realize a circuit design having a smaller electromagnetic interference.
In the electromagnetic interference analysis method according to the invention, furthermore, the circuit information obtained at the optimizing step may be displayed as optimized information.
Moreover, the invention provides an electromagnetic interference analysis apparatus including equivalent impedance information calculating means for calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and electromagnetic interference noise calculating means for calculating an electromagnetic interference noise based on the equivalent impedance information.
It is desirable that the equivalent impedance information calculating means should extract a chip area, a power pad position and power supply information from the circuit information and should extract a package type from the package information, and the electromagnetic interference noise calculating means should include estimating means for calculating and estimating equivalent impedance information based on the information thus extracted.
Moreover, it is desirable that the circuit information should include floor plan information.
It is desirable that the circuit information should include layout information.
It is desirable that the circuit information should include netlist information.
It is desirable that the netlist information should include circuit information on a function level.
It is desirable that the netlist information should include circuit information on a gate level.
It is desirable that the netlist information should include circuit information on a transistor level.
It is desirable that the equivalent impedance information calculating means should be capable of estimating a memory block as a capacitance from the circuit information so as to be executed.
It is desirable that the equivalent impedance information calculating means should include estimating means for estimating a capacitance in consideration of an activation ratio.
It is desirable that the equivalent impedance information calculating means should include means for estimating a resistance value from the circuit information.
It is desirable that the equivalent impedance information calculating means should include equivalent resistance calculating means for extracting circuit connection information from the circuit information, and furthermore, creating circuit connection information in which an active element is substituted for a predetermined resistance and calculating an equivalent resistance.
It is desirable that the equivalent impedance information calculating means should include resistance value estimating means for estimating a resistance value based on a chip area from the circuit information.
It is desirable that the equivalent impedance information calculating means should include means for changing inductance information for a wire length into a database, wire length calculating means for calculating the wire length from the circuit information and the package information, and extracting means for extracting the inductance information changed into the database from the wire length, thereby estimating an inductance.
It is desirable that the apparatus should include noise estimating means for estimating an EMI noise based on an equivalent impedance obtained by the equivalent impedance information calculating means.
It is desirable that the noise estimating means should include means for calculating a frequency response characteristic of the LSI from the equivalent impedance and the circuit information and estimating means for estimating an EMI noise of the LSI based on the frequency response characteristic.
It is desirable that the noise estimating means should include means for calculating an offset value based on a clock frequency and an estimated consumption power and means for multiplying the frequency response characteristic by the offset value.
It is desirable that the apparatus should further include correcting means for carrying out a correction in order to optimize an EMI noise based on the equivalent impedance thus obtained.
It is desirable that the correcting means should include correcting means for correcting a power terminal position, a package type and a wire length in order to correct the inductance estimated by the estimating means.
It is desirable that the correcting means should include capacitance correcting means for correcting a signal wiring capacitance such that a timing has no problem based on the capacitance estimated by the estimating means.
It is desirable that the correcting means for correcting a signal wiring capacitance should include correcting means for correcting a signal wiring width, a signal wiring length and a signal wiring path.
It is desirable that the correcting means should include power wiring layout correcting means for correcting a power wiring layout such that a voltage drop has no problem.
It is desirable that the power wiring layout correcting means should include correcting means for correcting a power path, a power wiring width and a power wiring length.
It is desirable that the correcting means should include capacitance correcting means for correcting a decoupling capacitance.
It is desirable that the correcting means should include connection relationship correcting means for correcting a connection relationship between a power supply and a capacitance.
Also in such an electromagnetic interference analysis apparatus, mainly, it is possible to easily carry out the EMI analysis by directly calculating an equivalent impedance from circuit information without calculating supply current information in the same manner as in the method. However, it is apparent that the electromagnetic interference analysis apparatus is also effective for the case in which the supply current information is calculated and the EMI analysis is carried out based on the supply current information.